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AS1115
64 LEDs, IC Interfaced LED Driver with Keyscan
D a ta s h e e t
1 General Description
The AS1115 is a compact LED driver for 64 single LEDs or 8 digits of 7-segments. The devices can be programmed via an IC compatible 2-wire interface. Every segment can be individually addressed and updated separately. Only one external resistor (RSET) is required to set the current. LED brightness can be controlled by analog or digital means. The devices include an integrated BCD code-B/HEX decoder, multiplex scan circuitry, segment and display drivers, and a 64-bit memory. Internal memory stores the shift register settings, eliminating the need for continuous device reprogramming. All outputs of the AS1115 can be configured for key readback. Key-switch status is obtained by polling for up to 64 keys while 16 keys can be used to trigger an interrupt. Additionally the AS1115 offers a diagnostic mode for easy and fast production testing. The AS1115 features a low shutdown current of typically 200nA, and an operational current of typically 350A. The number of digits can be programmed, the devices can be reset by software, and an external clock is also supported. The device is available in a QSOP-24 and the TQFN(4x4)-24 package.
2 Key Features
! ! ! ! ! ! ! ! ! ! ! ! !
3.4MHz IC-Compatible Interface Individual LED Segment Control Readback for 16 Keys plus Interrupt Open and Shorted LED Error Detection - Global or Individual Error Detection Hexadecimal- or BCD-Code for 7-Segment Displays 200nA Low-Power Shutdown Current (typ; data retained) Digital and Analog Brightness Control Display Blanked on Power-Up Drive Common-Cathode LED Displays Supply Voltage Range: 2.7 to 5.5V Software Reset Optional External Clock Package: - QSOP-24 - TQFN(4x4)-24
3 Applications
The AS1115 is ideal for seven-segment or dot matrix user interface displays of set-top boxes, VCRs, DVDplayers, washing machines, micro wave ovens, refrigerators and other white good or personal electronic applications.
Figure 1. Typical Application Diagram
VDD 2.7 to 5.5V 9.53k ISET SDA SCL IRQ
DIG0 to DIG7 SEGA-DP KEY0-7
8
8 8
AS1115
KEYA KEYB
SDA SCL P IRQ
GND
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4 Pinout
Pin Assignments
Figure 2. Pin Assignments (Top View)
22 SEGDP SEGD SCL SEGDP
18 SEG E 17 SEGC 16 VDD 15 SEGG 14 SEGB 13 SEGF
DIG1
DIG0
SDA
9
21 SEG E
18 SEGG
23 SEGD
20 SEGC
17 SEGB
15 SEGA
16 SEGF
13 ISET
19 VDD
14 SCL
24 IRQ
24 23 22 21 20 19
DIG2 1 DIG3 2 GND 3 DIG4 4 DIG5 5 DIG6 6
7 8
AS1115
DIG7 10 KEYB 12 KEYA 11 SDA 1 DIG0 2 DIG1 3 DIG2 4 DIG3 5 GND 6 DIG4 7 DIG5 8 DIG6 9
AS1115
Exposed Pad
10 11 12
KEYB
IRQ ISET
Pin Descriptions
Table 1. Pin Descriptions Pin Name SDA DIG0:DIG7 GND KEYA KEYB ISET SCL IRQ SEGA:SEGG , SEGDP VDD QSOP-24 TQFN(4x4)-24 1 2-5, 7-10 6 11 12 13 14 24 15-18, 20-23 19 22 Description
Serial-Data I/O. Open drain digital I/O IC data pin. Digit Drive Lines. Eight digit drive lines that sink current from the display 1, 2, 4, 5, 6, 7, common cathode. Keyscan detection optional, but must be polled by the 23, 24 Prozessor. 3 Ground. Keyscan Input. Keyscan lines for key readback. Can be used for self8 adressing. 9 Keyscan Input. Keyscan lines for key readback. Set Segment Current. Connect to VDD or a reference voltage through RSET to set the peak segment current (see Selecting RSET Resistor 10 Value and Using External Drivers on page 19). 11 Serial-Clock Input. 3.4MHz maximum rate. 21 Interupt Request Output. Open drain pin. Seven Segment and Decimal Point Drive Lines. 8 seven-segment 12-15, 17-20 drives and decimal point drive that source current to the display. 16 Positive Supply Voltage. Connect to +2.7 to +5.5V supply. Exposed Pad. This pin also functions as a heat sink. Solder it to a large Exposed Pad pad or to the circuit-board ground plane to maximize power dissipation.
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KEYA
DIG7
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5 Absolute Maximum Ratings
Stresses beyond those listed in Table 2 may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in Section 6 Electrical Characteristics on page 4 is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 2. Absolute Maximum Ratings Parameter VDD to GND Input Voltage Range All other pins to GND DIG0:DIG7 Sink Current SEGA:SEGG, SEGDP Humidity Electrostatic Discharge Digital outputs All other pins 100 88 30.5 -40 -55 +85 150 5 Min -0.3 -0.3 Max 7 7 or VDD + 0.3 500 100 85 1000 1000 Units V V mA mA % V V mA C/W C/W C C The reflow peak soldering temperature (body temperature) specified is in accordance with IPC/ JEDEC J-STD-020D "Moisture/ Reflow Sensitivity Classification for Non-Hermetic Solid State Surface Mount Devices". The lead finish for Pb-free leaded packages is matte tin (100% Sn). Non-condensing Norm: MIL 833 E method 3015 EIA/JESD78 on PCB, QSOP-24 package on PCB, TQFN(4x4)-24 package Notes
Current
Latch-Up Immunity Thermal Resistance JA Ambient Temperature Storage Temperature
Package Body Temperature
+260
C
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6 Electrical Characteristics
VDD = 2.7 to 5.5V, RSET = 9.53k, TAMB = -40 to +85C, typ. values @ TAMB = +25C, VDD = 5.0V (unless otherwise specified). Table 3. Electrical Characteristics Symbol VDD IDDSD Parameter Operating Supply Voltage Shutdown Supply Current All digital inputs at VDD or GND, TAMB = +25C RSET = open circuit. IDD fOSC IDIGIT ISEG ISEG ISEG Operating Supply Current Display Scan Rate Digit Drive Sink Current Segment Drive Source Current Segment Drive Current Matching Segment Drive Source Current All segments and decimal point on; ISEG = -40mA. 8 digits scanned VOUT = 0.65V VDD = 5.0V, VOUT = (VDD -1V) Average Current 0.48 320 -35 -41 3 47 -47 Conditions Min 2.7 0.2 0.35 335 0.96 Typ Max 5.5 2 0.6 mA kHz mA mA % mA Unit V A
Table 4. Logic Inputs/Outputs Characteristics Symbol IIH, IIL VIH VIL VOL(SDA) VKEYopen VKEYshort VOL(IRQ) VI Parameter Conditions Input Current SDA, SCL VIN = 0V or VDD Logic High Input Voltage SDA, SCL Logic Low Input Voltage SDA, SCL SDA Output Low Voltage ISINK = 3mA Keyscan Open Input Voltage Keyscan Short Input Voltage Interrupt Output Low Voltage ISINK = 3mA Hysteresis Voltage DIN, CLK, LD/CS Capacitive Load for Each Bus Line Open Detection Level Threshold Short Detection Level Threshold 0.7x VDD 0.05x VDD Min -1 0.7xVDD Typ Max 1 0.3xVDD 0.4 0.8xVDD 0.7x VDD 0.4 1 400 0.75x VDD 0.1x VDD 0.8x VDD 0.15x VDD Unit A V V V V V V V pF V V
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Table 5. Timing Characteristics Parameter SCL Frequency Bus Free Time Between STOP and tBUF START Conditions Hold Time for Repeated tHOLDSTART START Condition SCL Low Period tLOW SCL High Period tHIGH Setup Time for Repeated tSETUPSTART START Condition tSETUPDATA Data Setup Time fSCL tHOLDDATA tRISE(SCL) Data Hold Time 10 10 10 20 20 160 50 20 SCL Rise Time SCL Rise Time after Repeated START tRISE(SCL1) Condition and After an ACK Bit tFALL(SCL) SCL Fall Time tRISE(SDA) tFALL(SDA) SDA Rise Time SDA Fall Time Symbol Conditions Min 0.1 1.3 160 50 50 100 10 70 40 80 40 80 80 75 75 Typ Max 3.4 Unit MHz s ns ns ns ns ns ns ns ns ns ns ns ns ns ms
tSETUPSTOP STOP Condition Setup Time tSPIKESUP Pulse Width of Spike Suppressed Key Readback Debounce Time Note: The Min / Max values of the Timing Characteristics are guaranteed by design.
Figure 3. Timing Diagram
SDI tBUF tHIGH tHOLDSTART tR tLOW SCL tSETUPDATA tF
tHOLDSTART tSPIKESUP tSETUPSTOP tSETUPSTART
START STOP
tHOLDDATA
Repeated START
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7 Typical Operating Characteristics
RSET = 9.53k, VRset = VDD; Figure 4. Display Scan Rate vs. Supply Voltage;
780
Figure 5. Display Scan Rate vs. Temperature;
800
Vdd=2.7V Vdd=4V
760
780 760 740 720
Vdd=5V Vdd=5.5V
fosc (Hz) .
740
720
700
Tamb=-40C Tamb=+25C Tamb=+85C
fosc (Hz) .
2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
700 680 -40
680
-15
10
35
60
85
Vdd (V) Figure 6. Segment Current vs. Temperature;
60 50
Tamb (C) Figure 7. Segment Current vs. RSET;
50
Vseg Vseg Vseg Vseg = 4V; Vdd = 5V = 3V; Vdd = 5V = 2V; Vdd = 5V = 1.7V; Vdd = 2.7V
40
Iseg (mA) .
Iseg (mA) .
Vseg Vseg Vseg Vseg = 1.7V; Vdd = 2.7V = 1.7V; Vdd = 5V = 3V; Vdd = 5V = 4V; Vdd = 5V
40 30 20 10 0 -40
30
20
10
0 -15 10 35 60 85 0 10 20 30 40 50 60 70 80 90
Tamb (C) Figure 8. Segment Current vs. Supply Voltage;
60 50
Rset (kOhm) Figure 9. Segment Current vs. VDD; VRset = 2.8V
50 45 40 35
Vseg Vseg Vseg Vseg = 1.7V = 2V = 2.3V = 3.1V
Iseg (mA) .
Iseg (mA) .
Vseg = 1.7V Vseg = 3V Vseg = 4V
40 30 20 10 0 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
30 25 20 15 10 5 0 2.7 3 3.3 3.6 3.9 4.2
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Figure 10. VDIGIT vs. IDIGIT
0.4
Figure 11. Input High Level vs. Supply Voltage
3.5 3
0.3
2.5
Vdig (V) .
Vih (V) .
Vdd Vdd Vdd Vdd Vdd = 2.7V = 3.3V = 4V = 5V = 5.5V
2 1.5 1 0.5 0
0.2
0.1
0 0 0.05 0.1 0.15
Idig (A)
0.2
0.25
0.3
0.35
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
Vdd (V)
Figure 12. ISEG vs. VSEG; VDD = 5V
50 45 40 35
Rext Rext Rext Rext Rext = 10k = 13k = 18k = 30k = 56k
Figure 13. ISEG vs. VSEG; VDD = 4V
50 45 40 35
Rext Rext Rext Rext Rext = 8k2 = 10k = 13k = 18k = 30k
Iseg (mA) .
30 25 20 15 10 5 0 2 2.5 3 3.5 4 4.5 5
Iseg (mA) .
30 25 20 15 10 5 0 1 1.5 2 2.5 3 3.5 4
Vseg (V)
Vseg (V)
Figure 14. ISEG vs. VSEG; VDD = 3.3V
50 45 40 35
Rext Rext Rext Rext Rext = 6k8 = 8k2 = 10k = 13k = 18k
Figure 15. ISEG vs. VSEG; VDD = 2.7V
50 45 40 35
Rext Rext Rext Rext Rext = 4k7 = 5k6 = 6k8 = 10k = 13k
Iseg (mA) .
30 25 20 15 10 5 0 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2
Iseg (mA) .
30 25 20 15 10 5 0 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6
Vseg (V)
Vseg (V)
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8 Detailed Description
Block Diagram
Figure 16. Block Diagram (QSOP-24 Package)
Open/Short Detection + - 19 + VDD 13 ISET -
VDD
RSET
Oszillator
VDD
24 IRQ
8
15-18, 20-23 SEGA-G, SEGDP
Digital Control Logic
(PWM, Debounce,....)
8
2-5, 7-10 DIG0 to DIG7
VDD
2 VDD 14 SCL 1 SDA
11, 12 KEYA, KEYB
IC Interface
Registers
Data - Registers Control - Registers Scan - Registers
6 GND
AS1115
Figure 17. ESD Structure
valid for the pins: - IRQ - SCL - SDA - ISET - SEGA-G, SEGDP - KEYA, KEYB
VDD
VDD valid for the pins: - DIG0 to DIG7
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IC Interface
The AS1115 supports the IC serial bus and data transmission protocol in high-speed mode at 3.4MHz. The AS1115 operates as a slave on the IC bus. The bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions. Connections to the bus are made via the open-drain I/O pins SCL and SDA.
Figure 18. IC Interface Initialisation
1 8 9 1 8 9
0
0
0
0
0
A1
A0 R/W
D15 D14 D13 D12 D11 D10
D9
D8
Default values at power up: A1 = A0 = 0
Figure 19. Bus Protocol
SDI
MSB Slave Address R/W Direction Bit ACK from Receiver ACK from Receiver
SCL
1
2
6
7
8
9 ACK
1
2
3-8
8
9
ACK Repeat if More Bytes Transferred STOP or Repeated START
START
The bus protocol (as shown in Figure 19) is defined as: - Data transfer may be initiated only when the bus is not busy. - During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH will be interpreted as control signals. The bus conditions are defined as: - Bus Not Busy. Data and clock lines remain HIGH. - Start Data Transfer. A change in the state of the data line, from HIGH to LOW, while the clock is HIGH, defines a START condition. - Stop Data Transfer. A change in the state of the data line, from LOW to HIGH, while the clock line is HIGH, defines the STOP condition. - Data Valid. The state of the data line represents valid data, when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of data bytes transferred between START and STOP conditions is not limited and is determined by the master device. The information is transferred byte-wise and each receiver acknowledges with a ninth-bit. Within the IC bus specifications a high-speed mode (3.4MHz clock rate) is defined. - Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse that is associated with this acknowledge bit. A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an
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acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line HIGH to enable the master to generate the STOP condition. - Figure 19 on page 9 details how data transfer is accomplished on the IC bus. Depending upon the state of the R/ W bit, two types of data transfer are possible: - Master Transmitter to Slave Receiver. The first byte transmitted by the master is the slave address, followed by a number of data bytes. The slave returns an acknowledge bit after the slave address and each received byte. - Slave Transmitter to Master Receiver. The first byte, the slave address, is transmitted by the master. The slave then returns an acknowledge bit. Next, a number of data bytes are transmitted by the slave to the master. The master returns an acknowledge bit after all received bytes other than the last byte. At the end of the last received byte, a not-acknowledge is returned. The master device generates all of the serial clock pulses and the START and STOP conditions. A transfer is ended with a STOP condition or a repeated START condition. Since a repeated START condition is also the beginning of the next serial transfer, the bus will not be released. The AS1115 can operate in the following slave modes: - Slave Receiver Mode. Serial data and clock are received through SDA and SCL. After each byte is received, an acknowledge bit is transmitted. START and STOP conditions are recognized as the beginning and end of a serial transfer. Address recognition is performed by hardware after reception of the slave address and direction bit. - Slave Transmitter Mode. The first byte (the slave address) is received and handled as in the slave receiver mode. However, in this mode the direction bit will indicate that the transfer direction is reversed. Serial data is transmitted on SDA by the AS1115 while the serial clock is input on SCL. START and STOP conditions are recognized as the beginning and end of a serial transfer.
IC Device Self Addressing
If this feature is used, 2 of the 16 key readback nodes can be left open or shorted for self-addressing. This is done with KEYA together with SEGG and SEGF. This two nodes cannot be used for key-readback in this case. After startup all devices have the predefined adress 0000000. A single command for self-addressing will update all connected AS1115. This command has to be done after startup or everytime the AS1115 gets disconnected from the supply. The IC address definition must be done with fixed connection, since IC detection is excluded from debounce time of key registers.
IC Device Address Byte
The address byte (see Figure 20) is the first byte received following the START condition from the master device.
Figure 20. IC Device Address Byte
MSB 6 0 6 0 5 0 5 0 4 0 4 0 3 0 3 0 2 0 2 A1 1 0 1 A0 LSB R/W LSB R/W
predefined address:
0 MSB
updated address:
0
- The default slave address is factory-set to 0000000. - The two LSB bits of the address byte are the device select bits, A0 to A1, which can be set by the self-adress command after startup. A maximum of four devices with the same pre-set code can therefore be connected on the same bus at one time. - The last bit of the address byte (R/W) define the operation to be performed. When set to a 1 a read operation is selected; when set to a 0 a write operation is selected. Following the START condition, the AS1115 monitors the IC bus, checking the device type identifier being transmitted. Upon receiving the address code, and the R/W bit, the slave device outputs an acknowledge signal on the SDA line.
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Command Byte
The AS1115 operation, (see Table 6) is determined by a command byte (see Figure 21 on page 11).
Figure 21. Command Byte
MSB D15 6 D14 5 D13 4 D12 3 D11 2 D10 1 D09 LSB D08
Figure 22. Command and Single Data Byte Received
From Master to Slave From Slave to Master
0
AS1115 Registers
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
S
Slave Address
R/W A
Command Byte
A
Data Byte 1 Byte
Acknowledge from AS1115
A
P
Acknowledge from AS1115
0
Acknowledge from AS1115
0
0
Autoincrement Memory Word Address
Figure 23. Setting the Pointer to a Address Register to select a Data Register for a Read Operation
From Master to Slave From Slave to Master
0
AS1115 Registers
D15 D14 D13 D12 D11 D10 D9 D8
S
Slave Address
R/W A
Command Byte
A
P
Acknowledge from AS1115
0
Acknowledge from AS1115
0
Figure 24. Reading nBytes from AS1115
From Master to Slave From Slave to Master
Acknowledge from AS1115 0 Autoincrement Memory Word Address Acknowledge from Master 0 Stop reading Not Acknowledge from Master
1
n Bytes S Slave Address R/W A First Data Byte A Second Data Byte /A P
1
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
AS1115 Registers
Autoincrement to next address
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Initial Power-Up
On initial power-up, the AS1115 registers are reset to their default values, the display is blanked, and the device goes into shutdown mode. At this time, all registers should be programmed for normal operation.
Note: The default settings enable only scanning of one digit; the internal decoder is disabled and the Intensity Control Register (see page 17) is set to the minimum values.
Shutdown Mode
The AS1115 devices feature a shutdown mode, where they consume only 200nA (typ) current. Shutdown mode is entered via a write to the Shutdown Register (see Table 7). During shutdown mode the Digit-Registers maintain their data. Shutdown mode can either be used as a means to reduce power consumption or for generating a flashing display (repeatedly entering and leaving shutdown mode). For minimum supply current in shutdown mode, logic input should be at GND or VDD (CMOS logic level). When entering or leaving shutdown mode, the Feature Register is reset to its default values (all 0s) when Shutdown Register bit D7 (page 13) = 0.
Note: When Shutdown Register bit D7 = 1, the Feature Register is left unchanged when entering or leaving shutdown mode. If the AS1115 is used with an external clock, Shutdown Register bit D7 should be set to 1 when writing to the Shutdown Register.
Digit- and Control-Registers
The AS1115 devices contain 8 Digit-Registers,11 control-registers and 10 diagnostic-registers, which are listed in Table 6. All registers are selected using a 8-bit address word, and communication is done via the IC interface.
!
Digit Registers - These registers are realized with an on-chip 64-bit memory. Each digit can be controlled directly without rewriting the whole register contents. Control Registers - These registers consist of decode mode, display intensity, number of scanned digits, shutdown, display test and features selection registers.
!
Table 6. Register Address Map Type Register Address D15:D13 D12 D11 D10 D9 D8 D7:D0 Page
Digit 0 Digit 1
Digit Register
000 000 000 000 000 000 000 000 000 000 000 000 001 000 000 000 000 000 000
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1
0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0
0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0
0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 (see Table 20 on page 18) (see Table 14 on page 16) (see Table 18 on page 17) (see Table 18 on page 17) (see Table 18 on page 17) (see Table 18 on page 17) (see Table 8 on page 13) (see Table 17 on page 17) (see Table 19 on page 17) (see Table 7 on page 13) (see Table 9 on page 14, Table 10 on page 14 and Table 11 on page 15)
N/A N/A N/A N/A N/A N/A N/A N/A 13 17 17 12 N/A 18 13
Digit 2 Digit 3 Digit 4 Digit 5 Digit 6 Digit 7 Decode-Mode Global Intensity Scan Limit
Control Register
Shutdown Self-Adressing Feature Display Test Mode DIG0:DIG1 Intensity DIG2:DIG3 Intensity DIG4:DIG5 Intensity DIG6:DIG7 Intensity
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Table 6. Register Address Map Type Register Address D15:D13 D12 D11 D10 D9 D8 D7:D0 Page
Diagnostic Digit 0
Keyscan/Diagnostic Register
000 000 000 000 000 000 000 000 000 000
1 1 1 1 1 1 1 1 1 1
0 0 0 1 1 1 1 1 1 1
1 1 1 0 0 0 0 0 1 1
0 0 1 1 0 0 1 1 0 0
0 1 0 1 0 1 0 1 0 1
N/A N/A N/A N/A N/A N/A N/A N/A
Diagnostic Digit 1 Diagnostic Digit 2 Diagnostic Digit 3 Diagnostic Digit 4 Diagnostic Digit 5 Diagnostic Digit 6 Diagnostic Digit 7 KEYA KEYB
The Shutdown Register controls AS1115 shutdown mode.
Table 7. Shutdown Register Format (Address (HEX) = 0x0C)) Mode HEX Code Register Data D7 D6 D5 D4 D3 D2 D1 D0
Shutdown Mode, Reset Feature Register to Default Settings Shutdown Mode, Feature Register Unchanged Normal Operation, Reset Feature Register to Default Settings Normal Operation, Feature Register Unchanged
0x00 0x80 0x01 0x81
0 1 0 1
X X X X
X X X X
X X X X
X X X X
X X X X
X X X X
0 0 1 1
Decode Enable Register (0x09)
The Decode Enable Register sets the decode mode. BCD/HEX decoding (either BCD code - characters 0:9, E, H, L, P, and -, or HEX code - characters 0:9 and A:F) is selected by bit D2 (page 18) of the Feature Register. The Decode Enable Register is used to select the decode mode or no-decode for each digit. Each bit in the Decode Enable Register corresponds to its respective display digit (i.e., bit D0 corresponds to digit 0, bit D1 corresponds to digit 1 and so on). Table 9 lists some examples of the possible settings for the Decode Enable Register bits.
Note: A logic high enables decoding and a logic low bypasses the decoder altogether.
When decode mode is used, the decoder looks only at the lower-nibble (bits D3:D0) of the data in the Digit-Registers, disregarding bits D6:D4. Bit D7 sets the decimal point (SEG DP) independent of the decoder and is positive logic (bit D7 = 1 turns the decimal point on). Table 9 lists the code-B font; Table 10 lists the HEX font. When no-decode mode is selected, data bits D7:D0 of the Digit-Registers correspond to the segment lines of the AS1115. Table 11 shows the 1:1 pairing of each data bit to the appropriate segment line.
Table 8. Decode Enable Register Format Examples Decode Mode HEX Code D7 0 0 0 0 D6 0 0 0 0 Register Data D5 D4 D3 D2 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 D1 0 0 1 1 D0 0 1 1 1
No decode for digits 7:0 Code-B/HEX decode for digit 0. No decode for digits 7:1 Code-B/HEX decode for digit 0:2. No decode for digits 7:3 Code-B/HEX decode for digits 0:5. No decode for digits 7:6 Code-B/HEX decode for digits 0,2,5. No decode for digits 1, 3, 4, 6, 7
0x00 0x01 0x07 0x3F 0x25
0
0
1
0
0
1
0
1
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Figure 25. Standard 7-Segment LED Intensity Control and Inter-Digit Blanking
A F G E D C DP B
Table 9. Code-B Font Register Data Register Data Register Data CharCharCharacter D7 D6:D4 D3 D2 D1 D0 acter D7 D6: D4 D3 D2 D1 D0 acter D7 D6:D4 D3 D2 D1 D0
X
0
0
0
0
X
0
1
1
0
X
1
1
0
0
X
0
0
0
1
X
0
1
1
1
X
1
1
0
1
X
0
0
1
0
X
1
0
0
0
X
1
1
1
0
X
0
0
1
1
X
1
0
0
1
*
X
1
1
1
1
X
0
1
0
0
X
1
0
1
0
1
X
X
X
X
X
X
*
0
1
0
1
X
1
0
1
1
The decimal point can be enabled with every character by setting bit D7 = 1. Table 10. HEX Font
Register Data Register Data Register Data CharCharCharacter D7 D6:D4 D3 D2 D1 D0 acter D7 D6: D4 D3 D2 D1 D0 acter D7 D6:D4 D3 D2 D1 D0
X
0
0
0
0
X
0
1
1
0
X
1
1
0
0
X
0
0
0
1
X
0
1
1
1
X
1
1
0
1
X
0
0
1
0
X
1
0
0
0
X
1
1
1
0
X
0
0
1
1
X
1
0
0
1
*
X
1
1
1
1
X
0
1
0
0
X
1
0
1
0
1
X
X
X
X
X
X
*
0
1
0
1
X
1
0
1
1
The decimal point can be enabled with every character by setting bit D7 = 1.
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Table 11. No-Decode Mode Data Bits and Corresponding Segment Lines
Corresponding Segment Line
D7 DP
D6 A
D5 B
D4 C
D3 D
D2 E
D1 F
D0 G
IC Self Addressing
If this feature is used, 2 of the 16 key readback nodes can be left open or shorted for self-addressing. This is done with KEYA together with SEGG and SEGF. This two nodes cannot be used for key-readback in this case. After startup all devices have the predefined adress 0000000. A single command for selfaddressing will update all connected AS1115. This command has to be done after startup or everytime the AS1115 gets disconnected from the supply. The IC address definition must be done with fixed connection, since IC detection is excluded from debounce time of key registers.
Note: A short writes a logical "1" whereas an open writes a logical "0" as address bit. Table 12. Self Addressing Register (Address (HEX) = 0x2D))
Factory-set IC address User-set IC address
D7 X X
D6 X X
D5 X X
D4 X X
D3 X X
D2 X X
D1 X X
D0 0 1
Keyscan Register
These two registers contain the result of the keyscan input of the 16 keys. To ensure proper results the data in these registers are updated only if the logic data scanned is stable for 20ms (debounce time). A change of the data stored within these two registers is indicated by a logic low on the IRQ pin. The IRQ is high-impedance if a read operation on the key scan registers is started.
Table 13. LED Diagnostic Register Address Register HEX Address 0x1C 0x1D Key KEYA KEYB D7 D6 D5 Segment D4 D3 D2 D1 D0
DP
A
B
C
D
E
F
G
Note: If IC self addressing is used segment G&F of KEYA is used for the two LSB of the IC address. In this case these two nodes cannot be used as a key. Additionally the debounce time is disabled for these two bits. The data within the keyscan register is updated continuously during every cycle (1/10 of refresh rate). Therefore, to get a valid readback of keys it is recommended to read out the keyscan registers immediately after the IRQ is triggered.
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Display-Test Mode
The AS1115 can detect open or shorted LEDs. Readout of either open LEDs or short LEDs is possible, as well as a OR relation of open and short.
Note: All settings of the digit- and control-registers are maintained. Table 14. Testmode Register Summary D7 X D6 RSET_short D5 RSET_open D4 LED_global D3 LED_test D2 LED_open D1 LED_short D0 DISP_test
Table 15. Testmode Register Bit Description (Address (HEX) = 0x0F)) Addr: 0x0F Bit Bit Name Default Access Address D7:D0
D0
DISP_test
0
W
Optical display test. (Testmode for external visual test.) 0: Normal operation; 1: Run display test (All digits are tested independently from scan limit & shutdown register.) Starts a test for shorted LEDs. (Can be set together with D2) 0: Normal operation; 1: Activate testmode Starts a test for open LEDs. (Can be set together with D1) 0: Normal operation; 1: Activate testmode Indicates an ongoing open/short LED test 0: No ongoing LED test; 1: LED test in progress Indicates that the last open/short LED test has detected an error 0: No error detected; 1: Error detected Checks if external resistor RSET is open 0: RSET correct; 1: RSET is open Checks if external resistor RSET is shorted 0: RSET correct; 1: RSET is shorted Not used
D1 D2 D3 D4 D5 D6 D7
LED_short LED_open LED_test LED_global RSET_open RSET_short
0 0 0 0 0 0 0
W W R R R R -
LED Diagnostic Registers
These eight registers contain the result of the LED open/short test for the individual LED of each digit.
Table 16. LED Diagnostic Register Address Register HEX Address 0x14 0x15 0x16 0x17 Segment Digit D7 D6 D5 D4 D3 D2 D1 D0 Register HEX Address 0x18 0x19 0x1A 0x1B Segment Digit D7 D6 D5 D4 D3 D2 D1 D0
DIG0 DIG1 DP DIG2 DIG3
A
B
C
D
E
F
G
DIG4 DIG5 DP DIG6 DIG7
A
B
C
D
E
F
G
Note: If one or more short occures in the LED array, detection of individual LED fault could become ambiguous.
Intensity Control Register (0x0A)
The brightness of the display can be controlled by digital means using the Intensity Control Registers and by analog means using RSET (see Selecting RSET Resistor Value and Using External Drivers on page 19). The intensity can be controlled globally for all digits, or for each digit individually. The global intensity command will write intensity data to all four individual brightness registers, while the individual intesity command will only write to the associated individual intensity register.
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Display brightness is controlled by an integrated pulse-width modulator which is controlled by the lower-nibble of the Intensity Control Register. The modulator scales the average segment-current in 16 steps from a maximum of 15/16 down to 1/16 of the peak current set by RSET.
Table 17. Intensity Register Format Duty Cycle HEX Code MSB 0 0 0 0 0 0 0 0 Register Data D2 D1 LSB 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Duty Cycle HEX Code MSB 1 1 1 1 1 1 1 1 Register Data D2 D1 LSB 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1
1/16 (min on) 2/16 3/16 4/16 5/16 6/16 7/16 8/16
0xX0 0xX1 0xX2 0xX3 0xX4 0xX5 0xX6 0xX7
9/16 10/16 11/16 12/16 13/16 14/16 15/16 15/16 (max on)
0xX8 0xX9 0xXA 0xXB 0xXC 0xXD 0xXE 0xXF
Table 18. Intensity Register Address Register HEX Address 0x0A 0x10 0x11 0x12 0x13 Register Data Type Global Digit Digit Digit Digit D7:D4 X Digit 1 Intensity Digit 3 Intensity Digit 5 Intensity Digit 7 Intensity D3:D0 Global Intensity Digit 0 Intensity Digit 2 Intensity Digit 4 Intensity Digit 6 Intensity
Scan-Limit Register (0x0B)
The Scan-Limit Register controls which of the digits are to be displayed. When all 8 digits are to be displayed, the update frequency is typically 700Hz. If the number of digits displayed is reduced, the update frequency is increased. The frequency can be calculated using 10 x fOSC/(N+2), where N is the number of digits.
Note: To avoid differences in brightness this register should not be used to blank parts of the display (leading zeros). Table 19. Scan-Limit Register Format (Address (HEX) = 0x0B)) Scan Limit Register Data HEX Code D7:D3 D2 D1 D0 0xX0 X 0 0 0 0xX1 X 0 0 1 0xX2 X 0 1 0 0xX3 X 0 1 1 Scan Limit Register Data HEX Code D7:D3 D2 D1 D0 0xX4 X 1 0 0 0xX5 X 1 0 1 0xX6 X 1 1 0 0xX7 X 1 1 1
Display digit 0 only Display digits 0:1 Display digits 0:2 Display digits 0:3
Display digits 0:4 Display digits 0:5 Display digits 0:6 Display digits 0:7
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Feature Register (0x0E)
The Feature Register is used for enabling various features including switching the device into external clock mode, applying an external reset, selecting code-B or HEX decoding, enabling or disabling blinking, setting the blinking rate, and resetting the blink timing.
Note: At power-up the Feature Register is initialized to 0. Table 20. Feature Register Summary D7 D6 D5 D4 D3 D2 D1 D0
blink_ start
sync
blink_ freq_sel
blink_en
NU
decode_sel
reg_res
clk_en
Table 21. Feature Register Bit Descriptions (Address (HEX) = 0xXE) Addr: 0xXE Bit Feature Register Enables and disables various device features. Bit Name Default Access Bit Description External clock active. clk_en 0 R/W 0 = Internal oscillator is used for system clock. 1 = Pin CLK of the serial interface operates as system clock input. Resets all control registers except the Feature Register. 0 = Reset Disabled. Normal operation. reg_res 0 R/W 1 = All control registers are reset to default state (except the Feature Register) identically after power-up. Note: The Digit Registers maintain their data. Selects display decoding for the selected digits (Table 8 on page 13). decode_sel 0 = Enable Code-B decoding (see Table 9 on page 14). 0 R/W 1 = Enable HEX decoding (see Table 10 on page 14). NU Not used Enables blinking. blink_en 0 R/W 0 = Disable blinking. 1 = Enable blinking. Sets blink with low frequency (with the internal oscillator enabled): blink_freq_sel 0 = Blink period typically is 1 second (0.5s on, 0.5s off). 0 R/W 1 = Blink period is 2 seconds (1s on, 1s off). Synchronizes blinking on the rising edge of pin LD/CS. The multiplex and blink timing counter is cleared on the rising edge of pin LD/CS. By sync 0 R/W setting this bit in multiple devices, the blink timing can be synchronized across all the devices. Start Blinking with display enabled phase. When bit D4 (blink_en) is set, bit D7 determines how blinking starts. blink_start 0 R/W 0 = Blinking starts with the display turned off. 1 = Blinking starts with the display turned on.
D0
D1
D2 D3 D4 D5
D6
D7
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9 Typical Application
Selecting RSET Resistor Value and Using External Drivers
Brightness of the display segments is controlled via RSET. The current that flows into ISET defines the current that flows through the LEDs. Segment current is about 200 times the current in ISET. Typical values for RSET for different segment currents, operating voltages, and LED voltage drop (VLED) are given in Table 22 & Table 23. The maximum current the AS1115 can drive is 47mA. If higher currents are needed, external drivers must be used, in which case it is no longer necessary that the devices drive high currents.
Note: The display brightness can also be logically controlled (see Intensity Control Register (0x0A) on page 16). Table 22. RSET vs. Segment Current and LED Forward Voltage, VDD = 2.7V & 3.3V & 3.6V ISEG (mA) VLED
1.5V 2.0V 1.5V
VLED
2.0V 2.5V 1.5V
VLED
2.0V 2.5V 3.0V
40 30 20 10
5k 6.9k 10.7k 22.2k
4.4k 5.9k 9.6k 20.7k
6.7k 9.1k 13.9k 28.8k
6.4k 8.8k 13.3k 27.7k
5.7k 8.1k 12.6k 26k
7.5k 10.18k 15.6k 31.9k
7.2k 9.8k 15k 31k
6.6k 9.2k 14.3k 29.5k
5.5k 7.5k 13k 27.3k
VDD = 2.7V
VDD = 3.3V
Table 23. RSET vs. Segment Current and LED Forward Voltage, VDD = 4.0V & 5.0V ISEG (mA) VLED
1.5V 2.0V 2.5V 3.0V 3.5V 1.5V 2.0V
VDD = 3.6V
VLED
2.5V 3.0V 3.5V 4.0V
40 30 20 10
8.6k 8.3k 11.6k 11.2k 17.7k 17.3k 36.89k 35.7k
7.9k 7.6k 5.2k 10.8k 9.9k 7.8k 16.6k 15.6k 13.6k 34.5k 32.5k 29.1k
11.35k 15.4k 23.6k 48.9k
11.12k 15.1k 23.1k 47.8k
10.84k 10.49k 10.2k 9.9k 14.7k 14.4k 13.6k 13.1k 22.6k 22k 21.1k 20.2k 46.9k 45.4k 43.8k 42k
VDD = 4.0V
Calculating Power Dissipation
The upper limit for power dissipation (PD) for the AS1115 is determined from the following equation:
PD = (VDD x 5mA) + (VDD - VLED)(DUTY x ISEG x N) Where: VDD is the supply voltage. DUTY is the duty cycle set by intensity register (page 17). N is the number of segments driven (worst case is 8) VLED is the LED forward voltage ISEG = segment current set by RSET Dissipation Example: ISEG = 40mA, N = 8, DUTY = 15/16, VLED = 2.2V at 40mA, VDD = 5V PD = 5V(5mA) + (5V - 2.2V)(15/16 x 40mA x 8) = 0.865W (EQ 2) (EQ 3) (EQ 1)
Thus, for a TQFN(4x4)-24 package JA = +30.5C/W, the maximum allowed TAMB is given by:
TJ,MAX = TAMB + PD x JA = 150C = TAMB + 0.865W x 30.5C/W (EQ 4)
In this example the maximum ambient temperature must stay below 123.61C.
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8x8 Dot Matrix Mode
The application example in Figure 26 shows the AS1115 in the 8x8 LED dot matrix mode. The LED columns have common cathodes and are connected to the DIG0:7 outputs. The rows are connected to the segment drivers. Each of the 64 LEDs can be addressed separately. The columns are selected via the digits as listed in Table 6 on page 12. The Decode Enable Register (see page 13) must be set to `00000000' as described in Table 8 on page 13. Single LEDs in a column can be addressed as described in Table 11 on page 15, where bit D0 corresponds to segment G and bit D7 corresponds to segment DP.
Figure 26. Application Example as LED Dot Matrix Driver
VDD 2.7 to 5V 9.53k ISET SDA SCL IRQ GND DIG0 to DIG7 SEG A to G SEP DP Diode Arrangement
SDA SCL P IRQ
AS1115
Keyscan
The key readback of the AS1115 can be used either for push buttons as well as switches. If only a single key is pressed (shorted) at a time no additional diodes are required. If a detection of multiple simultaneous keystrokes is required diodes within the keypath, as shown in Figure 27, are required. Pressing multiple keys without the diodes would result in ambiguous results. Since KEYA and KEYB have independent inputs only keys on the same path are affected.
Figure 27. Keyscan Configuration
SEGA SEGB SEGC SEGD SEG E SEGF SEGG SEGDP
KEYA
KEYB IRQ Diodes are optional and only required if multiple keystrokes must be detected simultaneously. If IC Self-Adressing is used these two keys cannot be used for readback and must be either hard wired opened or shorted. A short writes a logical "1" whereas an open writes a logical "0" as address bit.
Supply Bypassing and Wiring
In order to achieve optimal performance the AS1115 should be placed very close to the LED display to minimize effects of electromagnetic interference and wiring inductance. Furthermore, it is recommended to connect a 10F and a 0.1F ceramic capacitor between pins VDD and GND to avoid power supply ripple (see Figure 26).
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10 Package Drawings and Markings
The AS1115 is available in the QSOP-24 package.
Figure 28. QSOP-24 Package
Symbol A A1 A2 b C D E E1 e h L
Min Max 1.35 1.75 0.10 0.25 1.37 1.57 0.20 0.30 0.19 0.25 8.55 8.74 5.79 6.20 3.81 3.99 0.635 BSC 0.22 0.49 0.40 1.27 0 8
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Figure 29. TQFN(4x4)-24 Package
19
20
21
22
23
24
18 17 16 15 14 13
1 2 3 4 5 6
12
11
10
9
8
7
m m
Symbol A A1 A3 b D E D2 E2
Min 0.50 0.00
Typ 0.55
Max 0.60 0.05
0.18
2.70 2.70
0.152REF 0.23 4.00BSC 4.00BSC 2.80 2.80
0.28
2.90 2.90
Symbol e L L1 aaa bbb ccc ddd eee
Min
0.30 0.00
Typ 0.50BSC 0.35
Max
0.40 0.10
0.10 0.10 0.10 0.05 0.08
Notes:Unilateral coplanarity zone applies to the exposed heat sink slug as well as the terminals.
1. Dimensioning and tolerancing conform to ASME Y14.5M-1994. 2. All dimensions are in millimeters; angles in degrees. 3. Dimension b applies to metallized terminal and is measured between 0.25mm and 0.30mm from terminal tip. Dimension L1 represents terminal full back from package edge up to 0.1mm is acceptable. 4. Coplanarity applies to the exposed heat slug as well as the terminal. 5. Radius on terminal is optional.
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11 Ordering Information
The devices are available as the standard products shown in Table 24.
Table 24. Ordering Information Part AS1115-BSST AS1115-BQFT Marking AS1115 ASSD Delivery Form Tape and Reel Tape and Reel Package QSOP-24 TQFN(4x4)-24
All devices are RoHS compliant and free of halogene substances.
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Copyrights
Copyright (c) 1997-2009, austriamicrosystems AG, Schloss Premstaetten, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered (R). All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. All products and companies mentioned are trademarks or registered trademarks of their respective companies.
Disclaimer
Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. austriamicrosystems AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by austriamicrosystems AG for each application. For shipments of less than 100 parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location. The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However, austriamicrosystems AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems AG rendering of technical or other services.
Contact Information
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Tobelbaderstrasse 30 A-8141 Unterpremstaetten - Graz, Austria Tel: +43 (0) 3136 500 0 Fax: +43 (0) 3136 525 01
For Sales Offices, Distributors and Representatives, please visit: http://www.austriamicrosystems.com/contact-us
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